The present invention relates to a semiconductor device. The invention relates to, for example, a technology effective when applied to a technology of mounting, on a mounting substrate, a wiring board having thereon a semiconductor chip via a ball to be coupled to a land placed on the back surface of the wiring board.
Japanese Patent Laid-Open No. 2007-81374 (Patent Document 1) describes a technology in which a plurality of bonding pads formed on a substrate are comprised of a plurality of NSMD (Non-Solder Mask Defined) bonding pads and a plurality of SMD (Solder Mask Defined) bonding pads alternately arranged on one surface of the substrate.
Japanese Patent Laid-Open No. 2010-245455 (Patent Document 2) describes the following technology. Described specifically, among two or more pads, a pad formed on a corner portion is covered, at a first peripheral edge on the side of the corner portion far from the center of the base material of the pad, with a solder resist. On the other hand, a second peripheral edge on the side closer to the center of the base material than the first periphery is exposed from the solder resist.
According to Japanese Patent Laid-Open No. 2009-21366 (Patent Document 3), a plurality of first electrode pads is placed in an area of the back surface of a wiring board overlapping with a semiconductor chip in a plan view and a plurality of second electrode pads is placed in an area not overlapping with the semiconductor chip in a plan view. At this time, the first electrode pads and the second electrode pads are exposed from an opening provided in an insulating film. The first electrode pads are covered, at the peripheral edge thereof, with an insulating film, while the profile of the second electrode pads is smaller than the opening portion.
Japanese Patent Laid-Open No. 2005-252074 (Patent Document 4) describes the following technology. Described specifically, a plurality of electrode pads placed on the back surface of a wiring board is exposed from an opening portion provided in an insulating film. The electrode pads include a first electrode pad having a profile smaller than the opening portion and a second electrode pad covered at the peripheral edge thereof with an insulating film. At this time, the second electrode pad is placed at least at a position most distant from a semiconductor chip.